This invention related generally to a radiation-hardened integrated circuit, and more specifically to an integrated circuit with a partially insulating layer between the active element and substrate to dissipate photogenerated carriers from the substrate.
Continued advances in the fabrication of electronic devices for use in integrated circuits have led to dramatic improvements in performance and decreases in the physical dimensions of active electronic devices. However, such devices have also become increasingly sensitive to logic upset from the collection of electron-hole pairs created by ionizing radiation which strikes the device substrate. A particular concern arises from cosmic radiation in a space environment or from fission fragments produced by the radioactive decay of contaminants found in typical packaging materials used in integrated circuit manufacturing. This phenomenon is commonly referred to as "single-event upset" (SEU).
The problem typically occurs in complementary logic circuits involving two semiconductor devices connected such that one device is either "on" or "off" while the other device is in the alternate state. Such a situation is discussed in S. Diehl et al., "Considerations for Single Event Immune VLSI Logic", IEEE Trans. Nuc. Sci., Vol. NS-30, No. 6, December 1983, pp. 4501-4507, where a cosmic ray strike near the depletion region of the "off" transistors of a CMOS RAM cell causes the collection of excess carriers which are swept out by the electric field of the drain and collected as an increase in reverse saturation current. This current charges the internal gate capacitance of the "on" transistors. If this gate voltage becomes sufficiently high, the logic circuit will switch.
Two approaches to reducing the likelihood of device upset from collected carriers are known: (1) the use of insulating regions under the active device area and (2) the use of dissipative circuit elements (capacitive and resistive) to reduce the rate of current transfer between the coupled inverters of a RAM cell.
The first approach removes the semiconductor region under the active device areas and replaces it with a wide bandgap insulating region. This insulating region acts as a barrier to charge flow, thereby reducing the amount of collected charge and, therefore, the likelihood of logic state upset. This approach may be implemented either by using an insulating substrate, e.g. silicon "on" sapphire, or by providing an insulating layer of a material such as silicon dioxide between the active device and the silicon substrate, e.g., silicon-on-insulator.
The use of a completely insulating barrier under the active device prevents photocurrents generated in the substrate from reaching the device. However, the insulating barrier also leads to other destabilizing effects. The ionizing radiation can induce a permanent positive charge near the silicon-sapphire interface, causing the formation of a permanent conducting channel in the transistors, independent of gate control (J. Repace et al., "The Effect of Process Variations on . . . Charge in Silicon-on-Sapphire Capacitors", IEEE Trans. Electron Devices, Vol. ED-25, No. 8, August 1978, pp. 978-982). In addition, the lack of electrical contact through the substrate between the FET devices causes the "kink" effect and photocurrent multiplication by a parasitic bipolar phototransistor.
As reported by J. Tihanyi et al., "Influence of the Floating Substrate Potential on the Characteristics of ESFI MOS Transistors", Solid-State Electronics, 1975, Vol. 18, pp. 309-314, impact ionization of carriers near the drain of a n-channel FET creates excess holes. For such a transistor operating in bulk silicon, these excess holes are extracted by the substrate bias. However, in silicon-on-insulator technologies, the dielectric acts as a barrier to current flow, preventing extraction of the hole current. The excess holes are repelled by the positive biases applied to the drain of the transistor and accumulate at the p-n junction in the source region. This accumulated positive charge forward biases the source-channel p-n junction, creating excess current and thereby preventing the realization of a unique drain current as a function of gate bias. This effect is intrinsic to the device under certain operating conditions, and does not require external ionizing radiation to create the effect.
G. Davis et al., "Transient Radiation Effects in SOI Memories", IEEE Trans. Nucl. Sci., NS-32, No. 6, December 1985, pp. 4432-4437, reports an additional destabilizing effect of SOI MOSFET caused by current multiplication by a parasitic bipolar phototransistor action that occurs within the MOSFET. Although the amount of charge that is collected in SOI technology is reduced to the thickness of the device active regions (which regions are much smaller than the substrate thickness), the current from the active regions that is collected is amplified by the parasitic phototransistor action, thereby negating the insulating intent of the SOI structure.
To prevent the kink effect and other anomalies resulting from the use of a fully insulting layer under the active device regions, a patterned buried oxide layer has been proposed. T. Kamins et al., "Patterned implanted buried-oxide transistor structures", J. Appl. Phys. 60(1), 1 July 1986, pp. 423-426. This approach uses a buried silicon dioxide (insulating) layer under only the source and drain regions of FETs, allowing the extraction of hole currents resulting from impact ionization in the high-field regions near the FET drain (to eliminate the kink effect) and allowing resistive contact to the base of the parasitic bipolar transistor (to reduce its effect). However, since this approach does not shield the FET from substrate-generated photocurrents (the largest source of such photocurrents), it is not effective against SEU.
The other approach to reducing device upset relies on the insertion of a decoupling resistor in the polysilicon interconnections between the inverters in a CMOS RAM cell. In this approach, the excess photogenerated charge collected by the drain of the "off" transistor is delayed by the RC time constant of the interconnect-gate capacitor combination. For an RC time constant greater than the excess carrier lifetime, the excess charge recombines before destabilizing the logic state of the opposite inverter, thereby eliminating SEU. Since the dissipative element is part of the path for signal propagation in the integrated circuit, the RC time constant of the interconnect-gate capacitor also slows the desired propagation of logic signals, thereby slowing circuit operation without regard to the presence of ionizing radiation.
A related approach reported by Diehl et al. is to add sufficient capacitance at sensitive nodes to maintain ion-induced voltage transients below upset level. This technique tends to increase the surface area of the active device.